1. Field of the Invention
The present invention relates to an interface circuit and a binary data transfer method, which are used in various sorts of electronic apparatuses and communication terminals. More specifically, the present invention relates to the interface circuit and the binary data transfer method, which are suitable for transmitting and receiving binary data signals at high communication environment.
2. Description of the Related Art
An interface circuit for transmitting and receiving binary data compares a received data signal voltage with a reference voltage so as to judge whether a level of the received data is “0 (low level)” or “1 (high level)”. In general, a reference voltage “Vref” is fixed to a predetermined voltage between a signal level of “0” and a signal level of “1”.
However, in a case where the reference voltage Vref is fixed, if common noise produced between a signal line and a ground is mixed into an original data signal, a potential difference between the ground level of a transmission side and the ground level of a reception side arises, namely, a ground potential difference arises. As a result, there is such a problem that a noise margin is narrowed due to the above-mentioned ground potential difference. Accordingly, a technical solution has been proposed in which the reference voltage Vref on the transmission side is utilized also on the reception side. Also, JP-A-9-232923 has proposed such a technique of dynamically controlling the reference voltage Vref.
In accordance with this technical proposition, when a level of a received transfer signal is changed from a high level to a low level, or from the low level to the high level, an interface circuit detects the change in the level, and samples a potential of a state after the level has been changed. As a result, the interface circuit acquires thereinto information about a voltage variation with respect also to a transfer signal which contains the voltage variation arose in a transfer path. Then, the interface circuit separately controls a logical threshold value with respect to rising of the transfer signal to the high level at a leading edge, and a logical threshold value with respect to falling of the transfer signal to the low level at a trailing edge. As previously described, this technical proposition dynamically controls the reference voltage Vref.
However, in this technical proposition, a data signal is actually received on the reception side, and thereafter, the reference voltage Vref is set by employing a signal level of the received data signal. As a consequence, this technical proposition cannot be used in a case where the data signal is required to be captured by a storage means (flip-flop circuit etc.) before the reference voltage Vref is dynamically controlled at each of time instants. Accordingly, this technical proposition cannot achieve an effect of enlarging a noise margin. In accordance with this technical proposition, for instance, in such a data transfer region that an operating frequency is high, the noise margin is brought into a narrow state. As a result, this technical proposition is not suitably applied to a high speed operation.
A differential transfer system is a technique of enlarging a noise margin before data is received. In the differential transfer system, a data signal which is intended to be transferred and an inverted data signal whose logic state is inverted are paired, and transferred by using a pair of signal lines. As a result, the differential transfer system has a higher resistance to common noise which is applied to respective signal lines of the pair in a similar manner, so high-speed operation can be easily performed.
However, in order that the differential transfer system is properly used, the two signal lines must be wired in such a manner that influences of delays and noise on signals of two systems transferred through the respective signal lines are made equal to each other. This leads to such a problem that a degree of difficulty of the wiring becomes higher, which increases cost of the wiring.
Further, in order to perform a synchronous transfer, the interface circuit for transmitting and receiving the data must synchronize the timing of the clock for capturing the received data by the storage means (flip-flop circuits etc.) with the timing of the clock on the transmission side. As a result, in the region of the high operating frequency, such a circuit arrangement for taking the clocks in all of the storage means (flip-flop circuits etc.) at the same time is employed. Accordingly, there is such a problem that electro magnetic interference (EMI) causing a power supply noise and an electromagnetic wave failure is increased.